Most existing commercial LED epitaxial wafers are epitaxied through MOCVD. For a lack of substrate matching with GaN lattice, most GaN-based LED epitaxial wafers are epitaxied over substrates of other material through heterogeneous epitaxy. Some common heterogeneous epitaxial substrates include sapphire (Al2O3), silicon carbide (SiC), etc. In consideration of large lattice mismatch and thermal expansivity difference between GaN and substrate, it is impossible to directly grow high-quality GaN epitaxial structure. As shown in FIG. 1, in existing and conventional GaN-based LED epitaxial structure, two-step growth method is adopted. Taking sapphire substrate as example, first, grow one GaN nucleating bottom layer under low-temperature environment (400° C.-700° C.). Under low-temperature environment, a two-dimensional layered growth is impossible, but a GaN nucleating seed can be formed to provide nucleating conditions for further high-quality two-dimensional layered growth; then, rise temperature to above 1000° C. and form a high-quality GaN layer structure with appropriate growth rate and VIII ratio; last, continuously grow an n-GaN layer, a MQW active layer and a p-GaN layer via epitaxy over the high-quality and undoped GaN structure layer to form a complete GaN-based LED epitaxial structure.
The two-step growth method can solve such problems as poor GaN crystallization quality and large warping stress resulted from large lattice mismatch and thermal expansivity difference between substrate and GaN and is widely applied in commercial scale production. Despite above achievements, this epitaxy method also has some problems. For example, the low-temperature GaN nucleating layer and high-temperature non-doped GaN buffer layer, after growth, can only reach surface flatness of relative height difference at dozens of nm level, indicating that a higher quality of GaN crystallinity is not yet improved, which is particularly significant in high-power device fabrication. As GaN crystallinity quality at bottom layer cannot be further improved, film resistance of the n-GaN layer, MQW active layer and p-GaN layer formed over it through epitaxy cannot be further reduced. On the one hand, in large-size chip applications, e.g., in large-power devices of 45 mil*45 mil chip size, when 350 mA current is energized, the work voltage VF is generally 3.1V or above due to accumulative series connection of film resistance of the entire epitaxial structure, which greatly reduces photoelectric conversion efficiency and increases non-radiative recombination rate, generating more heat energy and shortening service life of power devices. On the other hand, to reduce LED production cost, more and more commercial productions have introduced epitaxy and chip processing technology at larger size, e.g., from existing 2-inch substrate and epitaxial wafer to 4-inch and even 6-inch ones, to increase output per unit time and reduce production cost. Substrate and epitaxial wafer at larger size may lead to larger wrapping and lattice stress due to lattice and thermal expansivity mismatch, which cannot form a good two-dimensional layered growth structure over the original 2-inch small size epitaxial wafer. Therefore, scale production of epitaxial wafer at larger size (e.g., 4-inch or above) is impossible due to such problems as poor crystallinity at GaN bottom layer, large surface roughness, low electrical yield after growth of complete structure, high probability of large work voltage VF and low wavelength yield.
To solve the above problems, Chinese patent CN201110451083.2 discloses an insert layer between high-temperature undoped GaN buffer layer and N-type GaN layer, and such insert layer is overlaid with an AlxGa1-xN layer, an InyAl1-yN or an AlxGa1-xN layer and an InyAl1-yN layer, in which, 0.1<x<1.0, and 0<y<0.25. Advantages of such insert layer include improvement of lateral movement of electron over N-type GaN layer, higher carrier injection efficiency, and effective reduction of film resistance and work voltage VF. However, it still cannot effectively solve wrapping and lattice stress from lattice mismatch and thermal mismatch.